A retargetable tool-suite for the design of application specific instruction set processors using a machine description language

This paper presents BURAQ, a DSP development framework, which aims at optimizing cost, efficiency and turn around time of System-On-Chip development. BURAQ accepts an Instruction and Architecture description (IAD) file that represents the DSP and its instruction set at a higher level of abstraction, in a proprietary language. The system then synthesizes a complete hardware description of the processor core, along with accompanying tools i.e. ILP Assembler, Linker and Instruction Set Simulator. The synthesized processor core is composed of a processor kernel, registers, addressing units and functional units. A user friendly IDE for the above mentioned framework has also been developed and it allows easy specification and detailed analysis of the target architecture. Hence BURAQ allows a platform for hardware/software Co-Simulation of a DSP. Co-Simulation is a very powerful tool for early design space exploration and thus reducing production cost and development time of SOC architectures. The effectiveness of BURAQ was verified with a successful modeling of Texas Instruments’ TMS320C6x and StarCore’s SC140.